Semiconductor cube structures comprising three-dimensional arrays of integrated circuit chips have emerged as an important packaging approach having high density electronic interconnect. A typical three-dimensional cube structure consists of multiple integrated circuit chips adhesively secured together as a monolithic stack structure. A metallization pattern is often provided directly on at least one side surface of the monolithic stack structure for interconnecting the integrated circuit chips in the stack and for electrical connection of the stack to external circuitry. The metallization pattern can include both individual contacts and bussed contacts, along with multi-level wiring.
Current cube technology incorporates a final wafer metallization level, known as the transfer metal level, at wafer processing. For each integrated circuit chip, this transfer metal level connects selected chip contacts to the kerf region. Conventional cube processing requires that the transfer metal be subsequently covered by an insulator and an appropriate adhesive. The wafer is then diced, and the integrated circuit chips are stacked and laminated together to form the cube structure with the transfer metals of the chips aligned to at least one common face. This cube face is subsequently lapped and polished to expose the transfer metal leads. A layer of insulating material is deposited on the cube face and via T-connects are formed so as to connect to the transfer metal leads extending to the cube face. A metallization level is then formed on the cube face, electrically coupled to the via T-connects.
Lithographic requirements for forming the via T-connects should be such that there is sufficient alignment and overlay capability to "capture" the transfer metal leads extending to the common cube face without electrically shorting to buried kerf structures or to an adjacent integrated circuit chip in the stack. Unfortunately, due to process variations, "capturing" of transfer metal leads can often require a large via T-connect overlay requirement and a large via T-connect size requirement, both of which can carry an undesirably high via T-connect to die shorting probability. The present invention addresses these constraints of the existing art with a transfer metal having a transverse cross-sectional configuration that provides significant relaxation in via T-connect lithographic alignment, overlay and photoresist patterning requirements.